The new chip design presents a new approach to communication between a computer’s cores, or processors.
“This approach, called the core-to-core communication acceleration framework, improves communication performance by two to 12 times,” said Yan Solihin, an N.C. State professor and co-author of the study, in a press release. “In other words, the execution times — from start to finish — are twice as fast or faster.”
The study’s researchers said when it comes to dealing with large amounts of computational data, the traditional way of communicating between cores is inefficient.
Michael Kowolenko, a researcher at N.C. State, said computers are often slowed down by the amount of information they need to process and the chip can improve processing speeds.
“So if you can increase the efficiency of how you put information in and out of a chip by decreasing the path length, or opening up the freeway so to speak, the machine can go much faster,” he said.
The chip’s design — which includes new built-in hardware — replaces a slower software-based method for communication between cores.
The new hardware will be more efficient in communicating information between cores, which will increase processing speeds for the computer.
At the center of the chip’s design is a queue management device that performs the task of managing communication between cores without the need for time-consuming software instructions.
